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	<id>https://wiki.ixheim.de/index.php?action=history&amp;feed=atom&amp;title=Central_Processor</id>
	<title>Central Processor - Versionsgeschichte</title>
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	<updated>2026-05-17T15:40:17Z</updated>
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		<id>https://wiki.ixheim.de/index.php?title=Central_Processor&amp;diff=30719&amp;oldid=prev</id>
		<title>Mario.zimmermann: Die Seite wurde neu angelegt: „ [CPU Unit Count]   Number Of Processor Packages (Physical): 1   Number Of Processor Cores:              4   Number Of Logical Processors:           8  Intel C…“</title>
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		<updated>2022-01-21T09:07:15Z</updated>

		<summary type="html">&lt;p&gt;Die Seite wurde neu angelegt: „ [CPU Unit Count]   Number Of Processor Packages (Physical): 1   Number Of Processor Cores:              4   Number Of Logical Processors:           8  Intel C…“&lt;/p&gt;
&lt;p&gt;&lt;b&gt;Neue Seite&lt;/b&gt;&lt;/p&gt;&lt;div&gt; [CPU Unit Count]&lt;br /&gt;
  Number Of Processor Packages (Physical): 1&lt;br /&gt;
  Number Of Processor Cores:              4&lt;br /&gt;
  Number Of Logical Processors:           8&lt;br /&gt;
&lt;br /&gt;
Intel Core i7-3770 --------------------------------------------------------&lt;br /&gt;
&lt;br /&gt;
 [General Information]&lt;br /&gt;
  Processor Name:                         Intel Core i7-3770&lt;br /&gt;
  Original Processor Frequency:           3400.0 MHz&lt;br /&gt;
  Original Processor Frequency [MHz]:     3400&lt;br /&gt;
  CPU ID:                                 000306A9&lt;br /&gt;
  CPU Brand Name:                         Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz&lt;br /&gt;
  CPU Vendor:                             GenuineIntel&lt;br /&gt;
  CPU Stepping:                           E1&lt;br /&gt;
  CPU Code Name:                          Ivy Bridge-DT&lt;br /&gt;
  CPU Technology:                         22 nm&lt;br /&gt;
  CPU S-Spec:                             SR0PK&lt;br /&gt;
  CPU Thermal Design Power (TDP):         77.0 W&lt;br /&gt;
  CPU IA Cores Thermal Design Current (TDC): 112.0 A&lt;br /&gt;
  CPU GT Cores Thermal Design Current (TDC): 50.0 A&lt;br /&gt;
  CPU Power Limits (Max):                 Power = Unlimited, Time = 8.00 sec&lt;br /&gt;
  CPU Power Limit 1 (Long Duration)/Processor Base Power (PBP): Power = 77.00 W, Time = 1.00 sec [Locked]&lt;br /&gt;
  CPU Power Limit 2 (Short Duration)/Maximum Turbo Power (MTP): Power = 96.25 W, Time = Unlimited [Locked]&lt;br /&gt;
  CPU Max. Junction Temperature (Tj,max): 105 °C&lt;br /&gt;
  CPU Type:                               Production Unit&lt;br /&gt;
  CPU Platform:                           Socket H2 (LGA1155)&lt;br /&gt;
  Microcode Update Revision:              21&lt;br /&gt;
  Number of CPU Cores:                    4&lt;br /&gt;
  Number of Logical CPUs:                 8&lt;br /&gt;
 [Operating Points]&lt;br /&gt;
  CPU LFM (Minimum):                      1600.0 MHz = 16 x 100.0 MHz&lt;br /&gt;
  CPU HFM (Base):                         3400.0 MHz = 34 x 100.0 MHz&lt;br /&gt;
  CPU Turbo Max:                          3900.0 MHz = 39 x 100.0 MHz [Locked]&lt;br /&gt;
  Turbo Ratio Limits:                     39x (1-2c), 38x (3c), 37x (4c)&lt;br /&gt;
  CPU Current:                            3633.6 MHz = 37 x 98.2 MHz @ 1.1259 V&lt;br /&gt;
  CPU Bus Type:                           Intel Direct Media Interface (DMI) v2.0&lt;br /&gt;
  Maximum DMI Link Speed:                 5.0 GT/s&lt;br /&gt;
  Current DMI Link Speed:                 5.0 GT/s&lt;br /&gt;
  Number of Overclocking Bins:            4&lt;br /&gt;
 [Cache and TLB]&lt;br /&gt;
  L1 Cache:                               Instruction: 4 x 32 KBytes, Data: 4 x 32 KBytes&lt;br /&gt;
  L2 Cache:                               Integrated: 4 x 256 KBytes&lt;br /&gt;
  L3 Cache:                               8 MBytes&lt;br /&gt;
  Instruction TLB:                        2MB/4MB Pages, Fully associative, 8 entries&lt;br /&gt;
  Data TLB:                               4 KB Pages, 4-way set associative, 64 entries&lt;br /&gt;
 [Standard Feature Flags]&lt;br /&gt;
  FPU on Chip                             Present&lt;br /&gt;
  Enhanced Virtual-86 Mode                Present&lt;br /&gt;
  I/O Breakpoints                         Present&lt;br /&gt;
  Page Size Extensions                    Present&lt;br /&gt;
  Time Stamp Counter                      Present&lt;br /&gt;
  Pentium-style Model Specific Registers  Present&lt;br /&gt;
  Physical Address Extension              Present&lt;br /&gt;
  Machine Check Exception                 Present&lt;br /&gt;
  CMPXCHG8B Instruction                   Present&lt;br /&gt;
  APIC On Chip / PGE (AMD)                Present&lt;br /&gt;
  Fast System Call                        Present&lt;br /&gt;
  Memory Type Range Registers             Present&lt;br /&gt;
  Page Global Feature                     Present&lt;br /&gt;
  Machine Check Architecture              Present&lt;br /&gt;
  CMOV Instruction                        Present&lt;br /&gt;
  Page Attribute Table                    Present&lt;br /&gt;
  36-bit Page Size Extensions             Present&lt;br /&gt;
  Processor Number                        Not Present&lt;br /&gt;
  CLFLUSH Instruction                     Present&lt;br /&gt;
  Debug Trace and EMON Store              Not Present&lt;br /&gt;
  Internal ACPI Support                   Present&lt;br /&gt;
  MMX Technology                          Present&lt;br /&gt;
  Fast FP Save/Restore (IA MMX-2)         Present&lt;br /&gt;
  Streaming SIMD Extensions               Present&lt;br /&gt;
  Streaming SIMD Extensions 2             Present&lt;br /&gt;
  Self-Snoop                              Present&lt;br /&gt;
  Multi-Threading Capable                 Present&lt;br /&gt;
  Automatic Clock Control                 Present&lt;br /&gt;
  IA-64 Processor                         Not Present&lt;br /&gt;
  Signal Break on FERR                    Present&lt;br /&gt;
  Virtual Machine Extensions (VMX)        Not Present&lt;br /&gt;
  Safer Mode Extensions (Intel TXT)       Not Present&lt;br /&gt;
  Streaming SIMD Extensions 3             Present&lt;br /&gt;
  Supplemental Streaming SIMD Extensions 3 Present&lt;br /&gt;
  Streaming SIMD Extensions 4.1           Present&lt;br /&gt;
  Streaming SIMD Extensions 4.2           Present&lt;br /&gt;
  AVX Support                             Present&lt;br /&gt;
  Fused Multiply Add (FMA)                Not Present&lt;br /&gt;
  Carryless Multiplication (PCLMULQDQ)/GFMUL Present&lt;br /&gt;
  CMPXCHG16B Support                      Present&lt;br /&gt;
  MOVBE Instruction                       Not Present&lt;br /&gt;
  POPCNT Instruction                      Present&lt;br /&gt;
  XSAVE/XRSTOR/XSETBV/XGETBV Instructions Present&lt;br /&gt;
  XGETBV/XSETBV OS Enabled                Present&lt;br /&gt;
  Float16 Instructions                    Present&lt;br /&gt;
  AES Cryptography Support                Present&lt;br /&gt;
  Random Number Read Instruction (RDRAND) Present&lt;br /&gt;
  Extended xAPIC                          Not Present&lt;br /&gt;
  MONITOR/MWAIT Support                   Not Present&lt;br /&gt;
  Thermal Monitor 2                       Present&lt;br /&gt;
  Enhanced SpeedStep Technology           Present&lt;br /&gt;
  L1 Context ID                           Not Present&lt;br /&gt;
  Send Task Priority Messages Disabling   Present&lt;br /&gt;
  Processor Context ID                    Present&lt;br /&gt;
  Direct Cache Access                     Not Present&lt;br /&gt;
  TSC-deadline Timer                      Not Present&lt;br /&gt;
  Performance/Debug Capability MSR        Present&lt;br /&gt;
  IA32 Debug Interface Support            Not Present&lt;br /&gt;
  64-Bit Debug Store                      Not Present&lt;br /&gt;
  CPL Qualified Debug Store               Not Present&lt;br /&gt;
 [Extended Feature Flags]&lt;br /&gt;
  64-bit Extensions                       Present&lt;br /&gt;
  RDTSCP and TSC_AUX Support              Present&lt;br /&gt;
  1 GB large page support                 Not Present&lt;br /&gt;
  No Execute                              Present&lt;br /&gt;
  SYSCALL/SYSRET Support                  Present&lt;br /&gt;
  Bit Manipulation Instructions Set 1     Not Present&lt;br /&gt;
  Bit Manipulation Instructions Set 2     Not Present&lt;br /&gt;
  Advanced Vector Extensions 2 (AVX2)     Not Present&lt;br /&gt;
  Advanced Vector Extensions 512 (AVX-512) Foundation Not Present&lt;br /&gt;
  AVX-512 Prefetch Instructions           Not Present&lt;br /&gt;
  AVX-512 Exponential and Reciprocal Instructions Not Present&lt;br /&gt;
  AVX-512 Conflict Detection Instructions Not Present&lt;br /&gt;
  AVX-512 Doubleword and Quadword Instructions Not Present&lt;br /&gt;
  AVX-512 Byte and Word Instructions      Not Present&lt;br /&gt;
  AVX-512 Vector Length Extensions        Not Present&lt;br /&gt;
  AVX-512 52-bit Integer FMA Instructions Not Present&lt;br /&gt;
  Secure Hash Algorithm (SHA) Extensions  Not Present&lt;br /&gt;
  Software Guard Extensions (SGX) Support Not Present&lt;br /&gt;
  Supervisor Mode Execution Protection (SMEP) Present&lt;br /&gt;
  Supervisor Mode Access Prevention (SMAP) Not Present&lt;br /&gt;
  Hardware Lock Elision (HLE)             Not Present&lt;br /&gt;
  Restricted Transactional Memory (RTM)   Not Present&lt;br /&gt;
  Memory Protection Extensions (MPX)      Not Present&lt;br /&gt;
  Read/Write FS/GS Base Instructions      Present&lt;br /&gt;
  Enhanced Performance String Instruction Present&lt;br /&gt;
  INVPCID Instruction                     Not Present&lt;br /&gt;
  RDSEED Instruction                      Not Present&lt;br /&gt;
  Multi-precision Add Carry Instructions (ADX) Not Present&lt;br /&gt;
  PCOMMIT Instructions                    Not Present&lt;br /&gt;
  CLFLUSHOPT Instructions                 Not Present&lt;br /&gt;
  CLWB Instructions                       Not Present&lt;br /&gt;
  TSC_THREAD_OFFSET                       Not Present&lt;br /&gt;
  Platform Quality of Service Monitoring (PQM) Not Present&lt;br /&gt;
  Platform Quality of Service Enforcement (PQE) Not Present&lt;br /&gt;
  FPU Data Pointer updated only on x87 Exceptions Not Present&lt;br /&gt;
  Deprecated FPU CS and FPU DS            Not Present&lt;br /&gt;
  Intel Processor Trace                   Not Present&lt;br /&gt;
  PREFETCHWT1 Instruction                 Not Present&lt;br /&gt;
  AVX-512 Vector Bit Manipulation Instructions Not Present&lt;br /&gt;
  AVX-512 Vector Bit Manipulation Instructions 2 Not Present&lt;br /&gt;
  AVX-512 Galois Fields New Instructions  Not Present&lt;br /&gt;
  AVX-512 Vector AES                      Not Present&lt;br /&gt;
  AVX-512 Vector Neural Network Instructions Not Present&lt;br /&gt;
  AVX-512 Bit Algorithms                  Not Present&lt;br /&gt;
  AVX-512 Carry-Less Multiplication Quadword (VPCLMULQDQ) Not Present&lt;br /&gt;
  AVX-512 Vector POPCNT (VPOPCNTD/VPOPCNTQ) Not Present&lt;br /&gt;
  User-Mode Instruction Prevention        Not Present&lt;br /&gt;
  Protection Keys for User-mode Pages     Not Present&lt;br /&gt;
  OS Enabled Protection Keys              Not Present&lt;br /&gt;
  Wait and Pause Enhancements (WAITPKG)   Not Present&lt;br /&gt;
  Total Memory Encryption                 Not Present&lt;br /&gt;
  Key Locker                              Not Present&lt;br /&gt;
  57-bit Linear Addresses, 5-level Paging Not Present&lt;br /&gt;
  Read Processor ID                       Not Present&lt;br /&gt;
  Cache Line Demote                       Not Present&lt;br /&gt;
  MOVDIRI: Direct Stores                  Not Present&lt;br /&gt;
  MOVDIR64B: Direct Stores                Not Present&lt;br /&gt;
  ENQCMD: Enqueue Stores                  Not Present&lt;br /&gt;
  SGX Launch Configuration                Not Present&lt;br /&gt;
  Protection Keys for Supervisor-Mode Pages Not Present&lt;br /&gt;
  Control-Flow Enforcement Technology (CET) Shadow Stack Not Present&lt;br /&gt;
  AVX-512 4 x Vector Neural Network Instructions Word Variable Precision Not Present&lt;br /&gt;
  AVX-512 4 x Fused Multiply Accumulation Packed Single Precision Not Present&lt;br /&gt;
  Fast Short REP MOV                      Not Present&lt;br /&gt;
  User Interrupts                         Not Present&lt;br /&gt;
  AVX-512 VP2INTERSECT Support            Not Present&lt;br /&gt;
  AVX-512 FP16                            Not Present&lt;br /&gt;
  MD_CLEAR Support                        Present&lt;br /&gt;
  SERIALIZE                               Not Present&lt;br /&gt;
  Hybrid Processor                        Not Present&lt;br /&gt;
  TSX Suspend Load Address Tracking       Not Present&lt;br /&gt;
  Platform Configuration (PCONFIG)        Not Present&lt;br /&gt;
  Indirect Branch Restricted Speculation (IBRS), Indirect Branch Predictor Barrier (IBPB) Present&lt;br /&gt;
  Single Thread Indirect Branch Predictors (STIBP) Present&lt;br /&gt;
  L1D_FLUSH Support                       Present&lt;br /&gt;
  IA32_ARCH_CAPABILITIES MSR              Present&lt;br /&gt;
  IA32_CORE_CAPABILITIES MSR              Not Present&lt;br /&gt;
  Speculative Store Bypass Disable (SSBD) Present&lt;br /&gt;
  Control-Flow Enforcement Technology (CET) Indirect Branch Tracking Not Present&lt;br /&gt;
  Advanced Matrix Extensions (AMX) Tile Architecture Not Present&lt;br /&gt;
  Advanced Matrix Extensions (AMX) bfloat16 Support Not Present&lt;br /&gt;
  Advanced Matrix Extensions (AMX) 8-bit Integer Operations Not Present&lt;br /&gt;
  AVX (VEX-encoded) Vector Neural Network Instructions Not Present&lt;br /&gt;
  AVX-512 BFLOAT16 Instructions           Not Present&lt;br /&gt;
  Fast Zero-Length MOVSB                  Not Present&lt;br /&gt;
  Fast Short STOSB                        Not Present&lt;br /&gt;
  Fast Short CMPSB, SCASB                 Not Present&lt;br /&gt;
  History Reset                           Not Present&lt;br /&gt;
  Linear Address Masking                  Not Present&lt;br /&gt;
 [Vulnerability Mitigation Mechanisms]&lt;br /&gt;
  Rogue Data Cache Load (RDCL)            Susceptible&lt;br /&gt;
  Speculative Store Bypass (SSB)          Susceptible&lt;br /&gt;
  Microarchitectural Data Sampling (MDS)  Susceptible&lt;br /&gt;
  MCE on modifying code page size without TLB invalidation Susceptible&lt;br /&gt;
  Transactional Asynchronous Abort (TAA)  Affected&lt;br /&gt;
  Indirect Branch Restriction Speculation (IBRS) Not Supported&lt;br /&gt;
  RSB Alternate                           Not Supported&lt;br /&gt;
  L1D Flush on VM Entry Not Needed        Not Supported&lt;br /&gt;
  Energy Filtering Control                Not Supported&lt;br /&gt;
 [Enhanced Features]&lt;br /&gt;
  Thermal Monitor 1:                      Supported, Enabled&lt;br /&gt;
  Thermal Monitor 2:                      Supported, Enabled&lt;br /&gt;
  Enhanced Intel SpeedStep (GV3):         Supported, Enabled&lt;br /&gt;
  Bi-directional PROCHOT#:                Enabled&lt;br /&gt;
  Extended Auto-HALT State C1E:           Enabled&lt;br /&gt;
  MLC Streamer Prefetcher                 Supported, Enabled&lt;br /&gt;
  MLC Spatial Prefetcher                  Supported, Enabled&lt;br /&gt;
  DCU Streamer Prefetcher                 Supported, Enabled&lt;br /&gt;
  DCU IP Prefetcher                       Supported, Enabled&lt;br /&gt;
  Intel Dynamic Acceleration (IDA) Technology: Not Supported&lt;br /&gt;
  Intel Dynamic FSB Switching:            Not Supported&lt;br /&gt;
  Intel Turbo Boost Technology:           Supported, Enabled&lt;br /&gt;
  Programmable Ratio Limits:              Not Supported&lt;br /&gt;
  Programmable TDC/TDP Limits:            Supported, Disabled&lt;br /&gt;
  Hardware Duty Cycling:                  Not Supported&lt;br /&gt;
  Intel Speed Select:                     Not Supported&lt;br /&gt;
 [CPU IVB Features]&lt;br /&gt;
  Internal Graphics:                      Supported&lt;br /&gt;
  PEG Gen2 (5.0 GT/s):                    Supported&lt;br /&gt;
  DMI Gen2 (5.0 GT/s):                    Supported&lt;br /&gt;
  DMI Width:                              x2&lt;br /&gt;
  VT-d:                                   Supported&lt;br /&gt;
  ECC:                                    Not Supported&lt;br /&gt;
  DDR Overclocking:                       Not Supported&lt;br /&gt;
  IA Overclocking:                        Not Supported&lt;br /&gt;
  On-die DDR Write Vref Generation:       Supported&lt;br /&gt;
  DDR3L:                                  Not Supported&lt;br /&gt;
  DDR Write Vref:                         Supported&lt;br /&gt;
  Dual Channel:                           Supported&lt;br /&gt;
  2 DIMMS per Channel:                    Supported&lt;br /&gt;
  Camarillo Device:                       Not Supported&lt;br /&gt;
  Full ULT Information:                   Supported&lt;br /&gt;
  DDR 1N Mode Timings:                    Supported&lt;br /&gt;
  PEG x16 Port:                           Supported&lt;br /&gt;
  Link width upconfig:                    Supported&lt;br /&gt;
  DDR3 Frequency Support (133 MHz RefClk): 800 MHz (DDR3-1600)&lt;br /&gt;
  DDR3 Frequency Support (100 MHz RefClk): 800 MHz (DDR3-1600)&lt;br /&gt;
  Memory Size per Channel:                Unlimited (16GB)&lt;br /&gt;
  Additive Graphics:                      Supported&lt;br /&gt;
  Additive Graphics:                      Disabled&lt;br /&gt;
  PAVP:                                   Enabled&lt;br /&gt;
  HDCP:                                   Supported&lt;br /&gt;
  PCIe Gen 3:                             Supported&lt;br /&gt;
  Soft Bin:                               Not Supported&lt;br /&gt;
  SMT:                                    Supported&lt;br /&gt;
 [Memory Ranges]&lt;br /&gt;
  Maximum Physical Address Size:          36-bit (64 GBytes)&lt;br /&gt;
  Maximum Virtual Address Size:           48-bit (256 TBytes)&lt;br /&gt;
 [MTRRs]&lt;br /&gt;
  Range 0-800000000 (0MB-32768MB) Type:   Write Back (WB)&lt;br /&gt;
  Range 800000000-820000000 (32768MB-33280MB) Type: Write Back (WB)&lt;br /&gt;
  Range 820000000-830000000 (33280MB-33536MB) Type: Write Back (WB)&lt;br /&gt;
  Range E0000000-100000000 (3584MB-4096MB) Type: Uncacheable (UC)&lt;br /&gt;
  Range D0000000-E0000000 (3328MB-3584MB) Type: Uncacheable (UC)&lt;br /&gt;
  Range CC000000-D0000000 (3264MB-3328MB) Type: Uncacheable (UC)&lt;br /&gt;
  Range CB000000-CC000000 (3248MB-3264MB) Type: Uncacheable (UC)&lt;br /&gt;
  Range 82FE00000-830000000 (33534MB-33536MB) Type: Uncacheable (UC)&lt;/div&gt;</summary>
		<author><name>Mario.zimmermann</name></author>
	</entry>
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