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| Zeile 15: |
Zeile 15: |
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| | ==Umfassender Überblick== | | ==Umfassender Überblick== |
| − | [[TEN]] ----------------------------------------------------------------------- | + | [[TEN]] |
| − | | |
| − | [Current Computer]
| |
| − | Computer Name: TEN
| |
| − | [Operating System]
| |
| − | Operating System: Microsoft Windows 10 Professional (x64) Build 19044.1466 (21H2)
| |
| − | UEFI Boot: Not Present
| |
| − | Secure Boot: Not Capable
| |
| − | Hypervisor-protected Code Integrity (HVCI): Disabled
| |
| − | Virtual Machine Warning: Microsoft Hyper-V is active. Some results might not reflect real hardware !
| |
| − | | |
| − | Central Processor(s) ------------------------------------------------------
| |
| − | | |
| − | [CPU Unit Count]
| |
| − | Number Of Processor Packages (Physical): 1
| |
| − | Number Of Processor Cores: 4
| |
| − | Number Of Logical Processors: 8
| |
| − | | |
| − | Intel Core i7-3770 --------------------------------------------------------
| |
| − | | |
| − | [General Information]
| |
| − | Processor Name: Intel Core i7-3770
| |
| − | Original Processor Frequency: 3400.0 MHz
| |
| − | Original Processor Frequency [MHz]: 3400
| |
| − | CPU ID: 000306A9
| |
| − | CPU Brand Name: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz
| |
| − | CPU Vendor: GenuineIntel
| |
| − | CPU Stepping: E1
| |
| − | CPU Code Name: Ivy Bridge-DT
| |
| − | CPU Technology: 22 nm
| |
| − | CPU S-Spec: SR0PK
| |
| − | CPU Thermal Design Power (TDP): 77.0 W
| |
| − | CPU IA Cores Thermal Design Current (TDC): 112.0 A
| |
| − | CPU GT Cores Thermal Design Current (TDC): 50.0 A
| |
| − | CPU Power Limits (Max): Power = Unlimited, Time = 8.00 sec
| |
| − | CPU Power Limit 1 (Long Duration)/Processor Base Power (PBP): Power = 77.00 W, Time = 1.00 sec [Locked]
| |
| − | CPU Power Limit 2 (Short Duration)/Maximum Turbo Power (MTP): Power = 96.25 W, Time = Unlimited [Locked]
| |
| − | CPU Max. Junction Temperature (Tj,max): 105 °C
| |
| − | CPU Type: Production Unit
| |
| − | CPU Platform: Socket H2 (LGA1155)
| |
| − | Microcode Update Revision: 21
| |
| − | Number of CPU Cores: 4
| |
| − | Number of Logical CPUs: 8
| |
| − | [Operating Points]
| |
| − | CPU LFM (Minimum): 1600.0 MHz = 16 x 100.0 MHz
| |
| − | CPU HFM (Base): 3400.0 MHz = 34 x 100.0 MHz
| |
| − | CPU Turbo Max: 3900.0 MHz = 39 x 100.0 MHz [Locked]
| |
| − | Turbo Ratio Limits: 39x (1-2c), 38x (3c), 37x (4c)
| |
| − | CPU Current: 3633.6 MHz = 37 x 98.2 MHz @ 1.1259 V
| |
| − | CPU Bus Type: Intel Direct Media Interface (DMI) v2.0
| |
| − | Maximum DMI Link Speed: 5.0 GT/s
| |
| − | Current DMI Link Speed: 5.0 GT/s
| |
| − | Number of Overclocking Bins: 4
| |
| − | [Cache and TLB]
| |
| − | L1 Cache: Instruction: 4 x 32 KBytes, Data: 4 x 32 KBytes
| |
| − | L2 Cache: Integrated: 4 x 256 KBytes
| |
| − | L3 Cache: 8 MBytes
| |
| − | Instruction TLB: 2MB/4MB Pages, Fully associative, 8 entries
| |
| − | Data TLB: 4 KB Pages, 4-way set associative, 64 entries
| |
| − | [Standard Feature Flags]
| |
| − | FPU on Chip Present
| |
| − | Enhanced Virtual-86 Mode Present
| |
| − | I/O Breakpoints Present
| |
| − | Page Size Extensions Present
| |
| − | Time Stamp Counter Present
| |
| − | Pentium-style Model Specific Registers Present
| |
| − | Physical Address Extension Present
| |
| − | Machine Check Exception Present
| |
| − | CMPXCHG8B Instruction Present
| |
| − | APIC On Chip / PGE (AMD) Present
| |
| − | Fast System Call Present
| |
| − | Memory Type Range Registers Present
| |
| − | Page Global Feature Present
| |
| − | Machine Check Architecture Present
| |
| − | CMOV Instruction Present
| |
| − | Page Attribute Table Present
| |
| − | 36-bit Page Size Extensions Present
| |
| − | Processor Number Not Present
| |
| − | CLFLUSH Instruction Present
| |
| − | Debug Trace and EMON Store Not Present
| |
| − | Internal ACPI Support Present
| |
| − | MMX Technology Present
| |
| − | Fast FP Save/Restore (IA MMX-2) Present
| |
| − | Streaming SIMD Extensions Present
| |
| − | Streaming SIMD Extensions 2 Present
| |
| − | Self-Snoop Present
| |
| − | Multi-Threading Capable Present
| |
| − | Automatic Clock Control Present
| |
| − | IA-64 Processor Not Present
| |
| − | Signal Break on FERR Present
| |
| − | Virtual Machine Extensions (VMX) Not Present
| |
| − | Safer Mode Extensions (Intel TXT) Not Present
| |
| − | Streaming SIMD Extensions 3 Present
| |
| − | Supplemental Streaming SIMD Extensions 3 Present
| |
| − | Streaming SIMD Extensions 4.1 Present
| |
| − | Streaming SIMD Extensions 4.2 Present
| |
| − | AVX Support Present
| |
| − | Fused Multiply Add (FMA) Not Present
| |
| − | Carryless Multiplication (PCLMULQDQ)/GFMUL Present
| |
| − | CMPXCHG16B Support Present
| |
| − | MOVBE Instruction Not Present
| |
| − | POPCNT Instruction Present
| |
| − | XSAVE/XRSTOR/XSETBV/XGETBV Instructions Present
| |
| − | XGETBV/XSETBV OS Enabled Present
| |
| − | Float16 Instructions Present
| |
| − | AES Cryptography Support Present
| |
| − | Random Number Read Instruction (RDRAND) Present
| |
| − | Extended xAPIC Not Present
| |
| − | MONITOR/MWAIT Support Not Present
| |
| − | Thermal Monitor 2 Present
| |
| − | Enhanced SpeedStep Technology Present
| |
| − | L1 Context ID Not Present
| |
| − | Send Task Priority Messages Disabling Present
| |
| − | Processor Context ID Present
| |
| − | Direct Cache Access Not Present
| |
| − | TSC-deadline Timer Not Present
| |
| − | Performance/Debug Capability MSR Present
| |
| − | IA32 Debug Interface Support Not Present
| |
| − | 64-Bit Debug Store Not Present
| |
| − | CPL Qualified Debug Store Not Present
| |
| − | [Extended Feature Flags]
| |
| − | 64-bit Extensions Present
| |
| − | RDTSCP and TSC_AUX Support Present
| |
| − | 1 GB large page support Not Present
| |
| − | No Execute Present
| |
| − | SYSCALL/SYSRET Support Present
| |
| − | Bit Manipulation Instructions Set 1 Not Present
| |
| − | Bit Manipulation Instructions Set 2 Not Present
| |
| − | Advanced Vector Extensions 2 (AVX2) Not Present
| |
| − | Advanced Vector Extensions 512 (AVX-512) Foundation Not Present
| |
| − | AVX-512 Prefetch Instructions Not Present
| |
| − | AVX-512 Exponential and Reciprocal Instructions Not Present
| |
| − | AVX-512 Conflict Detection Instructions Not Present
| |
| − | AVX-512 Doubleword and Quadword Instructions Not Present
| |
| − | AVX-512 Byte and Word Instructions Not Present
| |
| − | AVX-512 Vector Length Extensions Not Present
| |
| − | AVX-512 52-bit Integer FMA Instructions Not Present
| |
| − | Secure Hash Algorithm (SHA) Extensions Not Present
| |
| − | Software Guard Extensions (SGX) Support Not Present
| |
| − | Supervisor Mode Execution Protection (SMEP) Present
| |
| − | Supervisor Mode Access Prevention (SMAP) Not Present
| |
| − | Hardware Lock Elision (HLE) Not Present
| |
| − | Restricted Transactional Memory (RTM) Not Present
| |
| − | Memory Protection Extensions (MPX) Not Present
| |
| − | Read/Write FS/GS Base Instructions Present
| |
| − | Enhanced Performance String Instruction Present
| |
| − | INVPCID Instruction Not Present
| |
| − | RDSEED Instruction Not Present
| |
| − | Multi-precision Add Carry Instructions (ADX) Not Present
| |
| − | PCOMMIT Instructions Not Present
| |
| − | CLFLUSHOPT Instructions Not Present
| |
| − | CLWB Instructions Not Present
| |
| − | TSC_THREAD_OFFSET Not Present
| |
| − | Platform Quality of Service Monitoring (PQM) Not Present
| |
| − | Platform Quality of Service Enforcement (PQE) Not Present
| |
| − | FPU Data Pointer updated only on x87 Exceptions Not Present
| |
| − | Deprecated FPU CS and FPU DS Not Present
| |
| − | Intel Processor Trace Not Present
| |
| − | PREFETCHWT1 Instruction Not Present
| |
| − | AVX-512 Vector Bit Manipulation Instructions Not Present
| |
| − | AVX-512 Vector Bit Manipulation Instructions 2 Not Present
| |
| − | AVX-512 Galois Fields New Instructions Not Present
| |
| − | AVX-512 Vector AES Not Present
| |
| − | AVX-512 Vector Neural Network Instructions Not Present
| |
| − | AVX-512 Bit Algorithms Not Present
| |
| − | AVX-512 Carry-Less Multiplication Quadword (VPCLMULQDQ) Not Present
| |
| − | AVX-512 Vector POPCNT (VPOPCNTD/VPOPCNTQ) Not Present
| |
| − | User-Mode Instruction Prevention Not Present
| |
| − | Protection Keys for User-mode Pages Not Present
| |
| − | OS Enabled Protection Keys Not Present
| |
| − | Wait and Pause Enhancements (WAITPKG) Not Present
| |
| − | Total Memory Encryption Not Present
| |
| − | Key Locker Not Present
| |
| − | 57-bit Linear Addresses, 5-level Paging Not Present
| |
| − | Read Processor ID Not Present
| |
| − | Cache Line Demote Not Present
| |
| − | MOVDIRI: Direct Stores Not Present
| |
| − | MOVDIR64B: Direct Stores Not Present
| |
| − | ENQCMD: Enqueue Stores Not Present
| |
| − | SGX Launch Configuration Not Present
| |
| − | Protection Keys for Supervisor-Mode Pages Not Present
| |
| − | Control-Flow Enforcement Technology (CET) Shadow Stack Not Present
| |
| − | AVX-512 4 x Vector Neural Network Instructions Word Variable Precision Not Present
| |
| − | AVX-512 4 x Fused Multiply Accumulation Packed Single Precision Not Present
| |
| − | Fast Short REP MOV Not Present
| |
| − | User Interrupts Not Present
| |
| − | AVX-512 VP2INTERSECT Support Not Present
| |
| − | AVX-512 FP16 Not Present
| |
| − | MD_CLEAR Support Present
| |
| − | SERIALIZE Not Present
| |
| − | Hybrid Processor Not Present
| |
| − | TSX Suspend Load Address Tracking Not Present
| |
| − | Platform Configuration (PCONFIG) Not Present
| |
| − | Indirect Branch Restricted Speculation (IBRS), Indirect Branch Predictor Barrier (IBPB) Present
| |
| − | Single Thread Indirect Branch Predictors (STIBP) Present
| |
| − | L1D_FLUSH Support Present
| |
| − | IA32_ARCH_CAPABILITIES MSR Present
| |
| − | IA32_CORE_CAPABILITIES MSR Not Present
| |
| − | Speculative Store Bypass Disable (SSBD) Present
| |
| − | Control-Flow Enforcement Technology (CET) Indirect Branch Tracking Not Present
| |
| − | Advanced Matrix Extensions (AMX) Tile Architecture Not Present
| |
| − | Advanced Matrix Extensions (AMX) bfloat16 Support Not Present
| |
| − | Advanced Matrix Extensions (AMX) 8-bit Integer Operations Not Present
| |
| − | AVX (VEX-encoded) Vector Neural Network Instructions Not Present
| |
| − | AVX-512 BFLOAT16 Instructions Not Present
| |
| − | Fast Zero-Length MOVSB Not Present
| |
| − | Fast Short STOSB Not Present
| |
| − | Fast Short CMPSB, SCASB Not Present
| |
| − | History Reset Not Present
| |
| − | Linear Address Masking Not Present
| |
| − | [Vulnerability Mitigation Mechanisms]
| |
| − | Rogue Data Cache Load (RDCL) Susceptible
| |
| − | Speculative Store Bypass (SSB) Susceptible
| |
| − | Microarchitectural Data Sampling (MDS) Susceptible
| |
| − | MCE on modifying code page size without TLB invalidation Susceptible
| |
| − | Transactional Asynchronous Abort (TAA) Affected
| |
| − | Indirect Branch Restriction Speculation (IBRS) Not Supported
| |
| − | RSB Alternate Not Supported
| |
| − | L1D Flush on VM Entry Not Needed Not Supported
| |
| − | Energy Filtering Control Not Supported
| |
| − | [Enhanced Features]
| |
| − | Thermal Monitor 1: Supported, Enabled
| |
| − | Thermal Monitor 2: Supported, Enabled
| |
| − | Enhanced Intel SpeedStep (GV3): Supported, Enabled
| |
| − | Bi-directional PROCHOT#: Enabled
| |
| − | Extended Auto-HALT State C1E: Enabled
| |
| − | MLC Streamer Prefetcher Supported, Enabled
| |
| − | MLC Spatial Prefetcher Supported, Enabled
| |
| − | DCU Streamer Prefetcher Supported, Enabled
| |
| − | DCU IP Prefetcher Supported, Enabled
| |
| − | Intel Dynamic Acceleration (IDA) Technology: Not Supported
| |
| − | Intel Dynamic FSB Switching: Not Supported
| |
| − | Intel Turbo Boost Technology: Supported, Enabled
| |
| − | Programmable Ratio Limits: Not Supported
| |
| − | Programmable TDC/TDP Limits: Supported, Disabled
| |
| − | Hardware Duty Cycling: Not Supported
| |
| − | Intel Speed Select: Not Supported
| |
| − | [CPU IVB Features]
| |
| − | Internal Graphics: Supported
| |
| − | PEG Gen2 (5.0 GT/s): Supported
| |
| − | DMI Gen2 (5.0 GT/s): Supported
| |
| − | DMI Width: x2
| |
| − | VT-d: Supported
| |
| − | ECC: Not Supported
| |
| − | DDR Overclocking: Not Supported
| |
| − | IA Overclocking: Not Supported
| |
| − | On-die DDR Write Vref Generation: Supported
| |
| − | DDR3L: Not Supported
| |
| − | DDR Write Vref: Supported
| |
| − | Dual Channel: Supported
| |
| − | 2 DIMMS per Channel: Supported
| |
| − | Camarillo Device: Not Supported
| |
| − | Full ULT Information: Supported
| |
| − | DDR 1N Mode Timings: Supported
| |
| − | PEG x16 Port: Supported
| |
| − | Link width upconfig: Supported
| |
| − | DDR3 Frequency Support (133 MHz RefClk): 800 MHz (DDR3-1600)
| |
| − | DDR3 Frequency Support (100 MHz RefClk): 800 MHz (DDR3-1600)
| |
| − | Memory Size per Channel: Unlimited (16GB)
| |
| − | Additive Graphics: Supported
| |
| − | Additive Graphics: Disabled
| |
| − | PAVP: Enabled
| |
| − | HDCP: Supported
| |
| − | PCIe Gen 3: Supported
| |
| − | Soft Bin: Not Supported
| |
| − | SMT: Supported
| |
| − | [Memory Ranges]
| |
| − | Maximum Physical Address Size: 36-bit (64 GBytes)
| |
| − | Maximum Virtual Address Size: 48-bit (256 TBytes)
| |
| − | [MTRRs]
| |
| − | Range 0-800000000 (0MB-32768MB) Type: Write Back (WB)
| |
| − | Range 800000000-820000000 (32768MB-33280MB) Type: Write Back (WB)
| |
| − | Range 820000000-830000000 (33280MB-33536MB) Type: Write Back (WB)
| |
| − | Range E0000000-100000000 (3584MB-4096MB) Type: Uncacheable (UC)
| |
| − | Range D0000000-E0000000 (3328MB-3584MB) Type: Uncacheable (UC)
| |
| − | Range CC000000-D0000000 (3264MB-3328MB) Type: Uncacheable (UC)
| |
| − | Range CB000000-CC000000 (3248MB-3264MB) Type: Uncacheable (UC)
| |
| − | Range 82FE00000-830000000 (33534MB-33536MB) Type: Uncacheable (UC)
| |
